Title :
Power-delay-area efficient modulo 2/sup n/+1 adder architecture for RNS
Author :
Patel, Rakesh A. ; Benaissa, M. ; Boussakta, Said ; Powell, N.
Author_Institution :
Dept. of Electron. & Electr. Eng., Univ. of Sheffield, UK
fDate :
3/3/2005 12:00:00 AM
Abstract :
A new modulo 2/sup n/+1 adder architecture based on the ELM addition algorithm is introduced. A simplification to an existing modulo 2/sup n/+1 addition algorithm is also presented. VLSI implementations using 130 nm CMOS technology demonstrate the superiority of the proposed adder over existing designs in the literature.
Keywords :
CMOS logic circuits; VLSI; adders; residue number systems; 130 nm; CMOS technology; ELM addition algorithm; RNS; VLSI implementations; adder architecture; power-delay-area efficient architecture;
Journal_Title :
Electronics Letters
DOI :
10.1049/el:20056837
