A 1.5 GHz All-Digital Spread-Spectrum Clock Generator

Author

Lin, Sheng-You ; Liu, Shen-Iuan

Author_Institution

Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan

Volume

44

Issue

11

fYear

2009

Firstpage

3111

Lastpage

3119

Abstract

An all-digital spread-spectrum clock generator (SSCG) has been fabricated in a 0.18 mum CMOS process. The analysis and design of this all-digital SSCG is presented. A mixed-signal phase and frequency detector is adopted to reduce the jitter, eliminate a digital adder, and also reduce latency. A Vernier time-to-digital converter (TDC) with time amplifiers is realized to enhance the timing resolution of the TDC and to track the frequency modulation in the SSCG. A digitally controlled oscillator with a resolution enhancement circuit is also presented. The measured electromagnetic interference reduction is 10.48 dB. The measured peak-to-peak jitter and rms jitter are 28.4 ps and 4 ps, respectively, at 1.5 GHz.

Keywords

CMOS digital integrated circuits; amplifiers; analogue-digital conversion; clocks; digital phase locked loops; electromagnetic interference; frequency modulation; jitter; oscillators; CMOS process; SSCG; TDC; Vernier time-digital converter; all-digital phase-locked loop; all-digital spread-spectrum clock generator; digitally controlled oscillator; electromagnetic interference reduction; frequency 1.5 GHz; frequency modulation; jitter; latency; mixed-signal phase-frequency detector; resolution enhancement circuit; time amplifier; Adders; CMOS process; Clocks; Delay; Electromagnetic measurements; Jitter; Phase detection; Phase frequency detector; Spread spectrum communication; Timing; All-digital phase-locked loop; electromagnetic interference; phase-locked loop; spread-spectrum clock generator; time-to-digital converter;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/JSSC.2009.2031577

Filename

5308584