Title :
ROM-Based Logic (RBL) Design: A Low-Power 16 Bit Multiplier
Author :
Paul, Bipul C. ; Fujita, Shinobu ; Okajima, Masaki
Author_Institution :
Toshiba America Res., Inc., San Jose, CA, USA
Abstract :
We present a ROM-based 16 times 16 multiplier for low-power applications. The design uses sixteen 4 times 4 ROM-based multiplier blocks followed by carry-save adders and a final carry-select adder (all ROM-based) to obtain the 32 bit output. All ROM blocks are implemented using single transistor ROM cells and eliminating identical rows and columns for optimizing the power and performance. Measurement results in 0.18 mum CMOS process show a 40% reduction in power over the conventional carry-save array multiplier when operated at its maximum frequency. The ROM-based design also provides 44% less delay than the array multiplier with a minimal increase (7.7%) in power. This demonstrates the low-power operation of the ROM-based multiplier also at higher frequencies.
Keywords :
CMOS integrated circuits; frequency multipliers; logic design; low-power electronics; read-only storage; CMOS process; ROM based logic design; conventional carry-save array multiplier; low-power applications; low-power multiplier; Adders; CMOS process; Delay; Frequency measurement; Logic circuits; Logic design; Logic functions; Logic gates; Power measurement; Read only memory; ROM-based carry-save adder; ROM-based carry-select adder; ROM-based logic (RBL) design; high-performance operation; low-power multiplier; low-power operation;
Journal_Title :
Solid-State Circuits, IEEE Journal of
DOI :
10.1109/JSSC.2009.2028928
