High performance picture-in-picture (PIP) IC using embedded DRAM technology

Author

Brett, Maik ; Wendel, Dirk

Author_Institution

Infineon Technol., Munich, Germany

Volume

45

Issue

3

fYear

1999

fDate

8/1/1999 12:00:00 AM

Firstpage

698

Lastpage

705

Abstract

In this paper the next generation of a low cost, high performance single-chip picture-in-picture IC is presented. This chip is produced in a 0.35 μ eDRAM technology and integrates a digital multistandard color decoder, embedded DRAM, A/D and D/A converters as well as a data slicer for caption services. The paper deals with the digital video signal processing for color decoding with asynchronous sampling and the compensation of the skew. A new algorithm for a jointline-free true frame display was developed. The chip allows a smooth scaling from 1/81 to 1/4 of full-screen picture size and implements a data compression algorithm for splitscreen modes

Keywords

CMOS digital integrated circuits; compensation; data compression; decoding; digital signal processing chips; image colour analysis; image sampling; integrated circuit layout; television receivers; video coding; 0.35 micron; A/D converters; D/A converters; PIP IC; asynchronous sampling; caption services; compensation; data compression algorithm; data slicer; digital multistandard color decoder; digital video signal processing; eDRAM technology; embedded DRAM; embedded DRAM technology; high performance picture-in-picture IC; jointline-free true frame display; skew; smooth scaling; splitscreen modes; Decoding; Displays; Filters; Frequency synchronization; Random access memory; Read-write memory; Signal processing; Signal processing algorithms; Signal resolution; Switches;

fLanguage

English

Journal_Title

Consumer Electronics, IEEE Transactions on

Publisher

ieee

ISSN

0098-3063

Type

jour

DOI

10.1109/30.793574

Filename

793574