Title :
Estimation of maximum currents in MOS IC logic circuits
Author :
Chowdhury, Shuvro ; Barkatullah, Javed Sabir
Author_Institution :
Dept. of Electr. & Comput. Eng., Univ. of Iowa, Iowa City, IA, USA
fDate :
6/1/1990 12:00:00 AM
Abstract :
The authors deal with estimating currents in nMOS/CMOS IC logic circuits at three levels of hierarchies: gate level, macro level, and power/ground distribution level. Models are developed for estimating currents in a macro-cell (macro) in response to input excitations. Algorithms are developed to estimate the maximum current requirement for a macro and to identify the input excitation at which the maximum current occurs. The macro currents are used to estimate the maximum currents in the segments of power (ground) distribution systems. Some of the algorithms provide tradeoff between runtime and quality of solutions. Experimental results are included
Keywords :
CMOS integrated circuits; fault location; integrated logic circuits; logic testing; CMOS; MOS IC logic circuits; gate level; macro level; maximum current estimation; nMOS; power/ground distribution level; Current density; Integrated circuit reliability; Integrated circuit technology; Logic circuits; MOS devices; Runtime; Semiconductor device modeling; Timing; Very large scale integration; Voltage;
Journal_Title :
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
