Title :
A cost effective HDTV decoder IC with integrated system controller, down converter, graphics engine and display processor
Author :
Duardo, Obed ; Da Graca, Paul ; Hosotan, Shiro ; Sugawa, Satoshi ; Jiang, Hong
Author_Institution :
Lucent Technol., Bell Labs., Murray Hill, NJ, USA
fDate :
8/1/1999 12:00:00 AM
Abstract :
A highly integrated second generation HDTV IC that supports MPEG-2, ATSC, BS4, and other standards is presented. It performs transport stream demultiplexing, video decoding, down conversion for 480I/P displays, display processing and 2D graphics. A full resolution output is provided for HDTV displays
Keywords :
CMOS digital integrated circuits; decoding; digital signal processing chips; display instrumentation; frequency convertors; high definition television; image resolution; video coding; 0.25 micron; 2D graphics; 480I/P displays; ATSC; BS4; HDTV displays; MPEG-2; SDRAM; cost effective HDTV decoder IC; display processor; down converter; graphics engine; integrated system controller; memory; second generation HDTV IC; standard cell CMOS technology; standards; transport stream demultiplexing; video decoding; Control systems; Costs; Decoding; Displays; Engines; Graphics; HDTV; High definition video; SDRAM; Video compression;
Journal_Title :
Consumer Electronics, IEEE Transactions on
