DocumentCode :
1249624
Title :
Global flow optimization in automatic logic design
Author :
Berman, C. Leonard ; Trevillyan, Louise H.
Author_Institution :
IBM Thomas J Watson Res. Center, Yorktown Heights, NY, USA
Volume :
10
Issue :
5
fYear :
1991
fDate :
5/1/1991 12:00:00 AM
Firstpage :
557
Lastpage :
564
Abstract :
A method for optimizing digital logic networks is described. This approach uses the techniques of global flow analysis to efficiently gather information about the relationship between different wires in a circuit and uses methods from network flow to use this information to optimize the circuit. It differs from earlier methods for optimization of multilevel logic networks in that valid rearrangements of signal connections depend on the maintenance of global circuit invariants. An algorithm which reduces the problem of finding small circuits in this equivalence class to the problem of finding a min-cut in an associated graph is described. This algorithm has been implemented and forms part of an automatic design system in use within IBM. The authors describe the results of experiments undertaken to evaluate the effect of the techniques
Keywords :
circuit layout CAD; graph theory; logic CAD; optimisation; CAD; automatic logic design; computer aided design; digital logic networks; flow optimization; global flow analysis; min-cut; Algorithm design and analysis; Automatic logic units; Boolean functions; Circuit synthesis; Design optimization; Flow graphs; High level languages; Intelligent networks; Logic design; Optimization methods;
fLanguage :
English
Journal_Title :
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
Publisher :
ieee
ISSN :
0278-0070
Type :
jour
DOI :
10.1109/43.79493
Filename :
79493
Link To Document :
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