DocumentCode :
1249636
Title :
A recursive technique for computing delays in series-parallel MOS transistor circuits
Author :
Caisso, Jean-Paul ; Cerny, Eduard ; Rumin, Nicholas C.
Author_Institution :
Dept. of Electr. Eng., McGill Univ., Montreal, Que., Canada
Volume :
10
Issue :
5
fYear :
1991
fDate :
5/1/1991 12:00:00 AM
Firstpage :
589
Lastpage :
595
Abstract :
An efficient recursive technique for computing the Elmore delay in series-parallel resistance-capacitance (RC) networks is presented. The time complexity of the algorithm is on the order of the number of resistors times the number of nodes to which the delay has to be computed. In this respect it is superior to other known methods, particularly to that of P.K. Chan Karplus. Although that algorithm is more general, the present method should be attractive given the fact that many VLSI MOS circuits are based on design styles which are restricted to series-parallel transistor networks, which, in particular, exclude bridges. A special type of series-parallel RC circuit occurs in interconnection networks driven by multiple sources. A variation on the first algorithm, which is especially useful in a hierarchical simulator, is presented for computing the Elmore delay in such networks
Keywords :
MOS integrated circuits; VLSI; circuit analysis computing; computational complexity; delays; Elmore delay; MOSFET circuits; VLSI MOS circuits; hierarchical simulator; interconnection networks; recursive technique; series-parallel RC circuit; series-parallel transistor networks; time complexity; Algorithm design and analysis; Bridge circuits; Circuit simulation; Computational modeling; Computer networks; Delay effects; MOSFETs; Multiprocessor interconnection networks; Resistors; Very large scale integration;
fLanguage :
English
Journal_Title :
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
Publisher :
ieee
ISSN :
0278-0070
Type :
jour
DOI :
10.1109/43.79496
Filename :
79496
Link To Document :
بازگشت