Test generation and verification for highly sequential circuits

A novel test procedure that exploits the structure of the combinational logic in the circuit as well as the sequential behavior of the circuit is presented. Initially, before test generation, separate sum-of-product representations of the complete or partial ON-sets and OFF-sets of each of the flip-flop inputs and primary outputs of the sequential circuit are extracted using the PODEM algorithm. Fast algorithms for state justification and state differentiation based on this representation are described. The algorithm developed for test generation is extended to verification of finite-state machines (FSMs). The algorithm for state differentiation based on the ON- and OFF-set representation is modified for verification purposes. The authors present experimental results that illustrate the superior performance of this approach as compared to previous approaches to FSM verification. They are able to verify examples with significantly more memory elements than previous approaches