An efficient microcode compiler for application specific DSP processors

Author

Goossens, Gert ; Rabaey, Jan ; Vandewalle, Joos ; De Man, Hugo

Author_Institution

Interuniv. Micro-Electron. Center, Leuven, Belgium

Volume

9

Issue

9

fYear

1990

fDate

9/1/1990 12:00:00 AM

Firstpage

925

Lastpage

937

Abstract

A computer program for microcode compilation for custom digital signal processors is presented. This tool is part of the CATHEDRAL II silicon compiler. The following optimization problems are highlighted: scheduling, hardware assignment, and loop folding. Efficient techniques to solve these problems are developed. This allows for the automatic synthesis of processor architectures which simultaneously exploit pipelining and parallelism. A demonstrator design is presented

Keywords

application specific integrated circuits; circuit layout CAD; digital signal processing chips; parallel architectures; pipeline processing; program compilers; CATHEDRAL II silicon compiler; application specific DSP processors; hardware assignment; loop folding; microcode compiler; optimization problems; parallelism; pipelining; processor architectures; scheduling; Application software; Computer architecture; Digital signal processing; Digital signal processors; Hardware; Parallel processing; Pipeline processing; Processor scheduling; Signal synthesis; Silicon compiler;

fLanguage

English

Journal_Title

Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on

Publisher

ieee

ISSN

0278-0070

Type

jour

DOI

10.1109/43.59069

Filename

59069