Unconstrained via minimization for topological multilayer routing

A theoretical study which allows determination of the minimum number of vias for realizable multilayer channel routing under a topological model is presented. The theory is sufficiently general to solve a variety of problems under different technological constraints, e.g. VLSI multilayer switchbox and channel routing, through-hole printed circuit board (PCB) channels, and single-layer routing. Topological routing is concerned with wire intersection but not area, zero-width wires and zero-area vias being assumed. Unconstrained via minimization (UVM) is not constrained to a prerouted topology. This paper presents restrictive cases of UVM, finding most to be NP-hard, but the case resulting from constraints of traditional switchbox or channel routing to be solvable in O(kn²), where k is the maximum number of pins of a net layer and n is the number of pins. The minimum number of vias for various switchbox and channel routing benchmarks are reported