Hole confinement MOS-gated Ge/sub x/Si/sub 1-x//Si heterostructures

Author

Garone, P.M. ; Venkataraman, V. ; Sturni, J.C.

Author_Institution

Dept. of Electr. Eng., Princeton Univ., NJ, USA

Volume

12

Issue

5

fYear

1991

fDate

5/1/1991 12:00:00 AM

Firstpage

230

Lastpage

232

Abstract

The confinement of carriers in a MOS-gated Ge/sub x/Si/sub 1-x/ heterostructure is numerically modeled. The structure uses a MOS gate to modulate the hole density at a buried Si/sub x//Ge/sub x/Si//sub 1-x/ interface. The number of holes in the well is modeled as a function of structure and gate bias. The hole confinement is then confirmed by capacitance-voltage and Hall measurements. Numerical modeling is used to predict the maximum number of carriers achievable at the interface as a function of the structural design, and clear experimental evidence for such carrier confinement is given.<>

Keywords

Ge-Si alloys; insulated gate field effect transistors; semiconductor device models; semiconductor junctions; semiconductor materials; silicon; CMOS; Ge/sub x/Si/sub 1-x/-Si; HIGFET; Hall measurements; MOS gate; MOSFET; capacitance-voltage measurements; carrier confinement; heterostructures; hole confinement; hole density modulation; numerical modeling; Aluminum alloys; Capacitance; Capacitive sensors; Carrier confinement; Germanium silicon alloys; Low voltage; MOSFET circuits; Numerical models; Scattering; Silicon germanium;

fLanguage

English

Journal_Title

Electron Device Letters, IEEE

Publisher

ieee

ISSN

0741-3106

Type

jour

DOI

10.1109/55.79566

Filename

79566