DocumentCode
12507
Title
Origin of Device Performance Enhancement of Junctionless Accumulation-Mode (JAM) Bulk FinFETs With High- 
Gate Spacers
Author
Ji Hun Choi ; Tae Kyun Kim ; Jung Min Moon ; Young Gwang Yoon ; Byeong Woon Hwang ; Dong Hyun Kim ; Seok-Hee Lee
Author_Institution
Dept. of Electr. Eng., Korea Adv. Inst. of Sci. & Technol., Daejeon, South Korea
Volume
35
Issue
12
fYear
2014
fDate
Dec. 2014
Firstpage
1182
Lastpage
1184
Abstract
In this letter, we investigated the junctionless accumulation-mode (JAM) bulk FinFETs with high-κ gate spacers showing enhanced device performance in SS, DIBL, and ON/OFF current ratio. We found that origin of the ON-state current enhancement was reduction of the initial energy barrier between the source and channel, and reason for the OFF-state current reduction was LG extension caused by the fringing field through high-κ gate spacers. The OFF-state leakage current decreased by over one order of magnitude. The ON-state current was remarkably enhanced by 180% over that of low-κ gate spacers. The high-κ gate spacer is indispensable for enhancing the performance of the JAM field-effect transistor in a sub 20-nm -gate length regime.
Keywords
MOSFET; high-k dielectric thin films; leakage currents; DIBL; JAM field-effect transistor; OFF-state current reduction; OFF-state leakage current; ON-state current enhancement; ON/OFF current ratio; SS; device performance enhancement; energy barrier reduction; high-κ gate spacers; junctionless accumulation-mode bulk FinFETs; low-κ gate spacers; Doping; Energy barrier; FinFETs; High K dielectric materials; Performance evaluation; Fringing field; JAM FET; fringing field; high- $kappa$ gate spacers; high-κ gate spacers; junctionless (JL) FET;
fLanguage
English
Journal_Title
Electron Device Letters, IEEE
Publisher
ieee
ISSN
0741-3106
Type
jour
DOI
10.1109/LED.2014.2364093
Filename
6936858
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