Title :
Behavioral model synthesis with Cones
Author :
Stroud, Charles E. ; Munoz, Ronald R. ; Pierce, David A.
Author_Institution :
AT&T Bell Lab., Naperville, IL, USA
fDate :
6/1/1988 12:00:00 AM
Abstract :
The Cones synthesis system for automatic generation of VLSI implementations is discussed. Named for the cones in sequential logic, Cones takes behavioral models written in C and produces gate-level implementations in technologies such as standard cells and programmable logic arrays or programmable logic devices. The overall design is produced faster, more efficiently, and with fewer errors. Designers are free to concentrate on functions, instead of on the details of the implementation technology.<>
Keywords :
VLSI; cellular arrays; circuit CAD; integrated logic circuits; logic CAD; software packages; Cones synthesis system; VLSI implementations; gate-level implementations; programmable logic arrays; programmable logic devices; sequential logic; standard cells; Boolean functions; Circuits; Hardware; Logic devices; Process design; Production; Programmable logic arrays; Programmable logic devices; Prototypes; Testing;
Journal_Title :
Design & Test of Computers, IEEE
