Abstract :
The data rate of the dynamic random access memory (DRAM) interface has been greatly increased to reduce the performance gap between the DRAM and the central processing unit (CPU). The data rate of double-data rate (DDR) synchronous DRAM (SDRAM) is now exceeding 266 Mb/s/pin while the packet-based RAMBUS DRAM is offering up to 1066 Mb/s/pin data rate. The difference in the data rate is mainly due to their different channel structures. These DRAM interface channels are basically multi-drop bus where a driver should drive multiple loads. The maximum data rate is determined by how the multiple loads are configured. The data rate of the DRAM interface channel has been greatly increased and is expected to exceed 2 Gb/s/pin in the near future. To achieve this goal, the physical interface such as the bus structure should be optimized to minimize the timing uncertainty. The I/O timing circuitry plays an important role in determining the maximum data rate. Thus, the, circuit design should also be focused on minimizing timing uncertainty
Keywords :
DRAM chips; system buses; timing circuits; CPU; I/O timing circuitry; SDRAM; bus structure; central processing unit; channel structures; circuit design; data rate; dynamic random access memory; high-speed DRAM interface; multi-drop bus; packet-based RAMBUS DRAM; synchronous DRAM; timing uncertainty minimisation; Bidirectional control; Circuits; Clocks; DRAM chips; Delay; Phase locked loops; Random access memory; Read-write memory; Timing; Uncertainty;
