Title :
Behavioral-level fault simulation
Author_Institution :
AT&T Bell Lab., Holmdel, NJ, USA
fDate :
6/1/1988 12:00:00 AM
Abstract :
An approach to fault simulation is presented in which behavioral fault models represent complex failures in VLSI designs. Errors are deliberately introduced into the description of a design that contains no faults. These errors can be fault values of variables that represent state or timing parameters, a faulty description that is substituted for part of the good description, or a combination of these. The algorithm guarantees accurate results by deferring the output assignments. The approach can also be used to detect and discard inconsistent output assignments. The algorithm has been implemented in Stanford University´s Sable simulator using the Adlib behavioral modeling language.<>
Keywords :
VLSI; digital simulation; fault location; logic testing; Adlib behavioral modeling language; Sable simulator; VLSI designs; behavioral fault models; fault simulation; output assignments; timing parameters; Algorithm design and analysis; Clocks; Counting circuits; Fault detection; Fault diagnosis; Hardware; Microprocessors; Reactive power; Testing; Timing;
Journal_Title :
Design & Test of Computers, IEEE
