Extremely scaled double-gate CMOS performance projections, including GIDL-controlled off-state current

Author

Fossum, Jerry G. ; Kim, Keunwoo ; Chong, Yan

Author_Institution

Dept. of Electr. Eng., Florida Univ., Gainesville, FL, USA

Volume

46

Issue

11

fYear

1999

fDate

11/1/1999 12:00:00 AM

Firstpage

2195

Lastpage

2200

Abstract

A simulation-based analysis of extremely scaled double-gate (DG) CMOS, emphasizing the effects of gate-induced drain leakage (GIDL) in DG MOSFETs, is described. Device and ring-oscillator simulations project an enormous performance potential for DG/CMOS, but also show how and why GIDL can be much more detrimental to off-state current in DG devices than in the single-gate counterparts. However, for asymmetrical (n⁺ and p⁺ polysilicon) gates, the analysis further shows that the GIDL effect can be controlled by tailoring the back (p⁺-gate) oxide thickness, which implies design optimization regarding speed as well as static power in DG/CMOS circuits

Keywords

CMOS integrated circuits; MOSFET; leakage currents; DG MOSFET; design optimization; device simulation; double-gate CMOS circuit; gate-induced drain leakage; off-state current; ring oscillator; scaling; Analytical models; CMOS process; CMOS technology; Capacitance; Circuit simulation; MOS devices; MOSFET circuits; Performance analysis; Semiconductor device modeling; Threshold voltage;

fLanguage

English

Journal_Title

Electron Devices, IEEE Transactions on

Publisher

ieee

ISSN

0018-9383

Type

jour

DOI

10.1109/16.796296

Filename

796296