Title :
Throughput advantages of asynchronous prober control
Author :
Powers, Robert J.
fDate :
6/1/1988 12:00:00 AM
Abstract :
Parallel testing of memories at the wafer-sort stage can offer significant throughput advantages. Accepted methods at this state involve synchronous prober control. A model is presented that shows how asynchronous prober control can increase throughput 36% over that possible with synchronous control.<>
Keywords :
integrated circuit testing; integrated memory circuits; asynchronous prober control; memory testing; parallel testing; wafer-sort stage; Costs; Flowcharts; Indexing; Needles; Packaging; Power generation economics; Probes; Semiconductor device modeling; Software testing; Throughput;
Journal_Title :
Design & Test of Computers, IEEE
