Title :
Single-chip interpolating time counter with 200-ps resolution and 43-s range
Author :
Kalisz, Jozef ; Szplet, Ryszard ; Pelka, Ryszard ; Poniecki, Andrzej
Author_Institution :
Mil. Tech. Acad., Warsaw, Poland
fDate :
8/1/1997 12:00:00 AM
Abstract :
In this paper, we present a design and test results of the interpolating time counter implemented on a single field programmable gate array (FPGA) chip. The counter contains two 6-bit time-to-digital converters (TDCs), each having 200-ps resolution (LSB) within 10 ns range, and the 32-bit, 100-MHz real-time counter, which is also used for frequency measurement. The utilization of the logic cells on the FPGA chip is 93%. The software correction of the TDC´s nonlinearity errors resulted in lowering the random error of the counter to 0.65 LSB or 129 ps (RMS)
Keywords :
CMOS logic circuits; analogue-digital conversion; counting circuits; field programmable gate arrays; integrated circuit testing; interpolation; 100 MHz; 43 s; delay verniers; digital delay lines; field programmable gate array chip; frequency measurement; logic cells; nonlinearity errors; random error; real-time counter; single-chip interpolating time counter; time-to-digital converters; wave pipelining; CMOS technology; Clocks; Counting circuits; Delay effects; Delay lines; Error correction; Field programmable gate arrays; Instruments; Quantization; Time measurement;
Journal_Title :
Instrumentation and Measurement, IEEE Transactions on
