A software solution for chip rate processing in CDMA wireless infrastructure

Author

Lange, Keld ; Blanke, Gero ; Rifaat, Rasekh

Volume

40

Issue

2

fYear

2002

fDate

2/1/2002 12:00:00 AM

Firstpage

163

Lastpage

167

Abstract

Third-generation cellular infrastructure requires extremely high-performance signal processing in the baseband receiver. Currently, chip rate processing is implemented using FPGA and ASIC technology. The use of a digital signal processor is explored for UTRA FDD systems with the goal of reducing cost and increasing flexibility. By combining chip rate and symbol rate processing within a single platform and taking advantage of the natural capacity of the air interface, load balancing can be performed, which reduces the amount of processing power needed, thereby reducing the cost of the receiver

Keywords

cellular radio; code division multiple access; digital signal processing chips; network interfaces; radio access networks; radio receivers; software engineering; spread spectrum communication; ASIC technology; CDMA wireless infrastructure; FPGA; UTRA FDD systems; Universal Terrestrial Radio Access; air interface; baseband receiver; chip rate processing; despreading; digital signal processor; high-performance signal processing; load balancing; receiver cost reduction; software solution; spreading; symbol rate processing; third-gene ration cellular infrastructure; time-division duplex system; 3G mobile communication; Base stations; Baseband; Computer architecture; Costs; Frequency; History; Land mobile radio; Multiaccess communication; Signal processing;

fLanguage

English

Journal_Title

Communications Magazine, IEEE

Publisher

ieee

ISSN

0163-6804

Type

jour

DOI

10.1109/35.983924

Filename

983924