Title :
Synchronous SRAM for digital signal processing applications
Author_Institution :
Lucent Technol., Holmdale, NJ
fDate :
3/27/1997 12:00:00 AM
Abstract :
A synchronous compact RAM that is designed for digital signal processing applications is presented. The small area of the RAM is achieved by using a dual global word line architecture. Circuit techniques which minimise the RAM clock cycle time and improve the performance of the sense amplifiers are also described. The circuits were implemented successfully in 0.5 μm CMOS technology
Keywords :
CMOS memory circuits; SRAM chips; memory architecture; signal processing; timing; 0.5 micron; CMOS technology; DSP applications; clock cycle time; compact static RAM; digital signal processing applications; dual global word line architecture; sense amplifiers; synchronous SRAM;
Journal_Title :
Electronics Letters
DOI :
10.1049/el:19970366
