Title :
ECL I/O buffers for BiCMOS integrated systems: a tutorial overview
Author :
Pickles, Neil S. ; Lefebvre, Martin C.
Author_Institution :
Dept. of Electron., Carleton Univ., Ottawa, Ont., Canada
fDate :
11/1/1997 12:00:00 AM
Abstract :
In this paper we describe the methodology for the design and layout of fast BiCMOS ECL (emitter-couped logic) I/O buffers. Principles of ECL circuit operation are described with emphasis on the NOR/OR gate and the bandgap voltage reference. A comparison of ECL 10 K and 100 K logic families is presented as well as complete designs for an input and output buffer. The pad macros are temperature- and supply-voltage-compensated and have nominal rise and fall times of 400 ps
Keywords :
BiCMOS logic circuits; buffer circuits; compensation; emitter-coupled logic; integrated circuit layout; logic design; logic gates; BiCMOS integrated systems; NOR/OR gate; bandgap voltage reference; emitter-couped logic I/O buffers; pad macros; supply-voltage-compensated interface circuit; temperature-compensated interface circuit; BiCMOS integrated circuits; Circuit noise; Design methodology; Impedance; Logic circuits; Logic devices; Photonic band gap; Resistors; Tutorial; Voltage;
Journal_Title :
Education, IEEE Transactions on
