DocumentCode :
1253444
Title :
A Parallel Multipole Accelerated 3-D Capacitance Simulator Based on an Improved Model
Volume :
15
Issue :
12
fYear :
1996
Firstpage :
1441
Lastpage :
1450
Abstract :
This paper gives an improved single-layer potential formula for extracting the parasitic capacitance of multiple conductors, embedded in the infinite or finite dielectrics, based on the MultiPole Accelerated (MPA) method. In fact, many capacitors should be considered to be bounded by a finite region. This indicates that the improvement is necessary to raise extraction accuracy. The nonuniform cube subdivision is used in the simulator. The reason for this is that it is an important base of further implementing the real adaptive calculation, for example h-version of the MPA. Also, it can save a lot of memory for ignoring most empty cubes. Only two lists of the cubes are used, thus simplifying the classification of five cube types. The simplified cell classification scheme eases book keeping in the parallel implementation. In developing a parallel MPA algorithm on the transputer network, a parallel machine of the MIMD type, we pay great attention to balancing workload and reducing communication for general nonuniform distribution of the particles. The results show that the total balance can be well achieved by balancing workload in every level of cubes. The pipeline communication mode shows higher efficiency if the processor number P used can well match problem size.
Keywords :
VLSI; capacitance; circuit CAD; circuit analysis computing; digital simulation; integrated circuit design; parallel algorithms; 3D capacitance simulator; VLSI; cell classification scheme; empty cubes; finite dielectrics; multiple conductors; multipole accelerated method; nonuniform cube subdivision; parallel MPA algorithm; parallel machine; parasitic capacitance; pipeline communication mode; real adaptive calculation; single-layer potential formula; transputer network; workload;
fLanguage :
English
Journal_Title :
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
Publisher :
ieee
ISSN :
0278-0070
Type :
jour
DOI :
10.1109/43.552078
Filename :
552078
Link To Document :
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