Design of efficient BIST test pattern generators for delay testing

Conventional built-in self-test (BIST) test pattern generators (TPGs) are designed to maximize stuck-at fault coverage in combinational circuits. Such TPGs often provide inadequate coverage of two-pattern tests which are required for the detection of delay faults. In this paper, theoretical results and procedures are presented to design efficient TPGs that ensure high two-pattern coverage for comprehensive delay testing of a circuit under test (CUT). First, new concepts particular to delay testing are identified and exploited to design efficient TPGs based on interleaved cyclic codes. A new concept of test cones is then introduced to further reduce the test length. Finally, the proposed procedures are used to design TPGs for delay testing of ISCAS´89 benchmark circuits and the results demonstrate their effectiveness