VLSI configurable delay commutator for a pipeline split radix FFT architecture

Author

García, Jesús ; Michell, Juan A. ; Burón, Angel M.

Author_Institution

Fac. de Ciencias, Cantabria Univ., Santander, Spain

Volume

47

Issue

11

fYear

1999

fDate

11/1/1999 12:00:00 AM

Firstpage

3098

Lastpage

3107

Abstract

This paper presents a full custom one-bit slice delay commutator for a pipeline split radix FFT (SRFFT) architecture, implemented using the true single-phase-clock (TSPC) circuit technique and a 1.0-μm CMOS technology. This circuit can be configured or all intermediate SRFFT computation levels for transforms of lengths up to N=2048, where N is power of two. The circuit has been tested up to 200 MHz, having a power consumption of 1.1 W at 5 V of power supply

Keywords

CMOS digital integrated circuits; VLSI; digital signal processing chips; fast Fourier transforms; parallel architectures; pipeline processing; 1.0 micron; 1.1 W; 5 V; CMOS; SRFFT architecture; TSPC circuit technique; VLSI configurable delay commutator; full custom one-bit slice delay commutator; pipeline split radix FFT architecture; power consumption; transforms; true single-phase-clock circuit technique; Arithmetic; CMOS technology; Circuit testing; Computer architecture; Delay; Discrete Fourier transforms; Parallel processing; Pipelines; Throughput; Very large scale integration;

fLanguage

English

Journal_Title

Signal Processing, IEEE Transactions on

Publisher

ieee

ISSN

1053-587X

Type

jour

DOI

10.1109/78.796442

Filename

796442