Thermal characterization of chip packages-evolutionary development of compact models

Author

Bar-Cohen, Avram ; Krueger, William B.

Author_Institution

Dept. of Mech. Eng., Minnesota Univ., Minneapolis, MN, USA

Volume

20

Issue

4

fYear

1997

fDate

12/1/1997 12:00:00 AM

Firstpage

399

Lastpage

410

Abstract

The expanded R_jc methodology, first proposed in 1989, makes it possible to extend the use of this common figure-of-merit to chip packages with nonisothermal cases. This proposal spurred considerable debate and contributed to renewed efforts to provide “compact” thermal models of single chip packages, for preliminary design, as well as for detailed numerical simulation of populated printed circuit boards. This presentation offers a review of the development of this modified R_jc methodology and its efficacy in replicating the chip, or junction, temperature predicted by detailed numerical simulation

Keywords

integrated circuit modelling; integrated circuit packaging; integrated circuit reliability; thermal resistance; chip packages; compact thermal models; figure-of-merit; junction temperature; nonisothermal cases; populated printed circuit boards; Electronic packaging thermal management; Integrated circuit packaging; Manufacturing; Numerical simulation; Printed circuits; Proposals; Surface resistance; Temperature; Thermal expansion; Thermal resistance;

fLanguage

English

Journal_Title

Components, Packaging, and Manufacturing Technology, Part A, IEEE Transactions on

Publisher

ieee

ISSN

1070-9886

Type

jour

DOI

10.1109/95.650929

Filename

650929