DocumentCode
1253787
Title
Intermetallic compound layer development during the solid state thermal aging of 63Sn-37Pb solder/Au-Pt-Pd thick film couples
Author
Vianco, Paul T. ; Stephens, John J. ; Rejent, Jerome A.
Author_Institution
Center for Solder Sci. & Technol., Sandia Nat. Labs., Albuquerque, NM, USA
Volume
20
Issue
4
fYear
1997
fDate
12/1/1997 12:00:00 AM
Firstpage
478
Lastpage
490
Abstract
A study was performed which examined the solid state, intermetallic compound layer growth kinetics between 63Sn-37Pb solder and a 76Au-21Pt-3Pd (wt.%) thick film conductor on 96% alumina substrates. A linear, multivariable regression analysis was used to assess the experimental data according to the following empirical relationship: x-x0=Atn exp(-ΔH/RT). A time exponent of n=0.78±0.08 was observed, suggesting that a combination of bulk diffusion and interface reaction mechanisms were responsible for layer growth. The apparent activation energy, ΔH, was 106⩾8 kJ/mol. Parallel aging experiments were performed on diffusion couples fabricated between 63Sn-37Pb solder and bulk alloy stock having the same Au-Pt-Pd composition as the thick film. Similar growth kinetic parameters were computed. Intermetallic compound layer growth was accelerated under thermal cycling and thermal shock conditions due to residual stresses generated by the thermal expansion mismatch between the solder and the ceramic substrate
Keywords
ageing; gold alloys; hybrid integrated circuits; integrated circuit interconnections; integrated circuit reliability; palladium; platinum alloys; soldering; thermal expansion; thermal shock; Al2O3; SnPb-AuPtPd-Al2O3; apparent activation energy; bulk diffusion; growth kinetics; hybrid microcircuits; interface reaction mechanisms; intermetallic compound layer; multivariable regression analysis; residual stresses; solder joints; solid state thermal aging; thermal cycling; thermal expansion mismatch; thermal shock; thick film conductor; time exponent; Aging; Conductive films; Intermetallic; Kinetic theory; Regression analysis; Solid state circuits; Substrates; Thermal expansion; Thermal stresses; Thick films;
fLanguage
English
Journal_Title
Components, Packaging, and Manufacturing Technology, Part A, IEEE Transactions on
Publisher
ieee
ISSN
1070-9886
Type
jour
DOI
10.1109/95.650938
Filename
650938
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