DocumentCode
1253947
Title
Analysis of testable PLA designs
Author
Zhu, Xl-An ; Breuer, Melvin A.
Author_Institution
Dept. of Electr. & Comput. Eng., Texas Univ., Austin, TX, USA
Volume
5
Issue
4
fYear
1988
Firstpage
14
Lastpage
28
Abstract
A framework is presented for evaluating methods of testing programmable logic arrays (PLAs), and the attributes of 25 test design methodologies are tabulated. PLA testing problems are first examined, and several test-generation algorithms are briefly described. Techniques for designing testable designs are examined, namely, special coding, parity checking, signature analysis, divide and conquer, and fully testable PLAs. The attributes that make a good testable design are then discussed. They fall into four categories: (1) testability characteristics; (2) effect on original design; (3) requirements of the application environment; and (4) design costs, i.e. how difficult it is to implement the technique.<>
Keywords
automatic testing; cellular arrays; integrated logic circuits; logic testing; PLA testing; divide and conquer; fully testable PLAs; parity checking; programmable logic arrays; signature analysis; special coding; test-generation algorithms; testability characteristics; testable PLA designs; Area measurement; Design methodology; Design optimization; Hardware; Logic arrays; Logic design; Logic testing; Programmable logic arrays; System testing; Time division multiplexing;
fLanguage
English
Journal_Title
Design & Test of Computers, IEEE
Publisher
ieee
ISSN
0740-7475
Type
jour
DOI
10.1109/54.7966
Filename
7966
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