Title :
Built-in test for RAMs
Author :
Bardell, Paul H., Jr. ; Mcanney, William H.
Author_Institution :
IBM, Poughkeepsie, NY, USA
Abstract :
A built-in test structure is described that is based on the ATS algorithmic test sequence, which provides the shortest possible test for stuck-at faults in a random-access memory (RAM). An initialization step has been added to ATS that allows the modified procedure to detect bit-rail faults. In the test mode, the memory address register is converted to a count-by-three circuit controlled by a four-latch test sequencer. A simple data-compare circuit is placed on the RAM outputs to detect faults.<>
Keywords :
automatic testing; integrated circuit testing; integrated memory circuits; random-access storage; ATS algorithmic test sequence; RAM; bit-rail faults; built-in test structure; count-by-three circuit; data-compare circuit; four-latch test sequencer; initialization step; memory address register; random-access memory; stuck-at faults; Built-in self-test; Circuit faults; Circuit testing; Decoding; Electrical fault detection; Fault detection; Logic testing; Random access memory; Read-write memory; Registers;
Journal_Title :
Design & Test of Computers, IEEE
