• DocumentCode
    1254682
  • Title

    A fast hierarchical algorithm for three-dimensional capacitance extraction

  • Author

    Shi, Weiping ; Liu, Jianguo ; Kakani, Naveen ; Yu, Tiejun

  • Author_Institution
    Dept. of Electr. Eng., Texas A&M Univ., College Station, TX, USA
  • Volume
    21
  • Issue
    3
  • fYear
    2002
  • fDate
    3/1/2002 12:00:00 AM
  • Firstpage
    330
  • Lastpage
    336
  • Abstract
    The authors present a new algorithm for computing the capacitance of three-dimensional electrical conductors of complex structures. The new algorithm is significantly faster and uses much less memory than previous best algorithms and is kernel independent. The new algorithm is based on a hierarchical algorithm for the n-body problem and is an acceleration of the boundary element method (BEM) for solving the integral equation associated with the capacitance extraction problem. The algorithm first adaptively subdivides the conductor surfaces into panels according to an estimation of the potential coefficients and a user-supplied error bound. The algorithm stores the potential coefficient matrix in a hierarchical data structure of size O(n), although the matrix is size n2 if expanded explicitly, where n is the number of panels. The hierarchical data structure allows the multiplication of the coefficient matrix with any vector in O (n) time. Finally, a generalized minimal residual algorithm is used to solve m linear systems each of size n × n in O(mn) time, where m is the number of conductors. The new algorithm is implemented and the performance is compared with previous best algorithms for the k × k bus example. The new algorithm is 60 times faster than FastCap and uses 1/80 of the memory used by FastCap. The results computed by the new algorithm are within 2.5% from that computed by FastCap. The new algorithm is 5 to 150 times faster than the commercial software QuickCap with the same accuracy
  • Keywords
    VLSI; boundary-elements methods; capacitance; circuit CAD; computational complexity; hierarchical systems; integrated circuit design; software performance evaluation; BEM; FastCap; VLSI design; boundary element method; capacitance extraction; complex structures; generalized minimal residual algorithm; hierarchical algorithm; hierarchical data structure; integral equation; multiplication; parasitic extraction; potential coefficients; three-dimensional electrical conductors; Acceleration; Boundary element methods; Capacitance; Conductors; Data mining; Data structures; Integral equations; Kernel; Linear systems; Vectors;
  • fLanguage
    English
  • Journal_Title
    Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0278-0070
  • Type

    jour

  • DOI
    10.1109/43.986426
  • Filename
    986426