• DocumentCode
    1254700
  • Title

    On diagnosing multiple stuck-at faults using multiple and single fault simulation in combinational circuits

  • Author

    Takahashi, Hiroshi ; Boateng, Kwame O. ; Saluja, Kewal K. ; Takamatsu, Yuzo

  • Author_Institution
    Dept. of Comput. Sci., Ehime Univ., Japan
  • Volume
    21
  • Issue
    3
  • fYear
    2002
  • fDate
    3/1/2002 12:00:00 AM
  • Firstpage
    362
  • Lastpage
    368
  • Abstract
    Diagnosing multiple stuck-at faults in combinational circuits using singleand multiple-fault simulation is proposed. The proposed method adds (removes) faults from a set of suspected faults depending on the result of multiple-fault simulation at a primary output agreeing (disagreeing) with the observed value. However, the faults that are added or removed from the set of suspected faults are determined using single-fault simulation. Diagnosis is carried out by repeated addition and removal of faults. The effectiveness of the diagnosis method is evaluated by experiments conducted on benchmark circuits and it is found to be substantially superior compared to the previous known solutions. The method proposed in this paper can be used as a powerful tool at the preprocessing stage of diagnosis in an electron-beam tester environment
  • Keywords
    automatic testing; combinational circuits; electron beam testing; fault simulation; integrated circuit testing; logic testing; benchmark circuits; combinational circuits; electron-beam tester; fault diagnosis; multiple stuck-at faults; multiple-fault simulation; Benchmark testing; Circuit faults; Circuit simulation; Circuit testing; Combinational circuits; Fault diagnosis; Fault location; Logic circuits; Logic testing; Random number generation;
  • fLanguage
    English
  • Journal_Title
    Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0278-0070
  • Type

    jour

  • DOI
    10.1109/43.986429
  • Filename
    986429