An 8-ns 256K ECL SRAM with CMOS memory array and battery backup capability

Author

Tran, Hai V. ; Scott, David B. ; Fung, Pak Kuen ; Havemann, Robert H. ; Eklund, Robert H. ; Ham, Thomas E. ; Haken, Roger A. ; SHAH, ASHWIN H.

Author_Institution

Texas Instrum. Inc., Dallas, TX, USA

Volume

23

Issue

5

fYear

1988

fDate

10/1/1988 12:00:00 AM

Firstpage

1041

Lastpage

1047

Abstract

The authors describe the first high-performance, high-density ECL SRAM (emitter-coupled-logic static random-access memory) compatible with battery backup techniques. The 256K device has a measured access time of 8 ns. Fabricated in a 0.8-μm BiCMOS process, the chip uses 117-μm ², full-CMOS, six-transistor memory cells and measures 6.5×8.15 mm². The design methodology described here illustrates the extent to which bipolar devices can be integrated into the periphery of a CMOS memory array. This integration was achieved through the use of a novel sensing scheme which provided three stages of bipolar differential sensing, with the first stage of sensing taking place directly on the bit lines

Keywords

BIMOS integrated circuits; emitter-coupled logic; integrated memory circuits; random-access storage; 0.8 micron; 256 kbit; 8 ns; BiCMOS process; CMOS memory array; ECL SRAM; access time; battery backup capability; bipolar differential sensing; emitter-coupled-logic; sensing scheme; six-transistor memory cells; static RAM; static random-access memory; Batteries; BiCMOS integrated circuits; CMOS process; CMOS technology; Immune system; Integrated circuit interconnections; MOS devices; Process design; Random access memory; Semiconductor device measurement;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.5922

Filename

5922