Title :
A 12-ns ECL I/O 256 K×1-bit SRAM using a 1-μm BiCMOS technology
Author :
Kertis, Robert A. ; Smith, Douglas D. ; Bowman, Terrance L.
Author_Institution :
Nat. Semicond. Corp., Puyallup, WA, USA
fDate :
10/1/1988 12:00:00 AM
Abstract :
An ECL (emitter-coupled-logic) I/O 256K×1-bit SRAM (static random-access memory) has been developed using a 1-μm BiCMOS technology. The double-level-poly, double-level-metal process produces 0.8-μm CMOS effective gate lengths and polysilicon emitter bipolar transistors. A zero-DC-power ECL-to-CMOS translation scheme has been implemented to interface the ECL periphery circuits to the CMOS decode and NMOS matrix. Low-impedance bit-line loads were used to minimize read access time. Minimization of bit-line recovery time after a write cycle is achieved through the use of a bipolar/CMOS write recovery method. Full-die simulations were performed using HSPICE on a CRAY-1
Keywords :
BIMOS integrated circuits; emitter-coupled logic; integrated memory circuits; random-access storage; 0.8 micron; 1 micron; 12 ns; 256 kbit; BiCMOS technology; ECL; HSPICE; SRAM; Si; bipolar/CMOS write recovery method; double-level-metal process; double-level-poly; effective gate lengths; emitter-coupled-logic; full die simulations; low impedance bit line loads; polysilicon emitter bipolar transistors; static RAM; static random-access memory; zero DC power ECL/CMOS translation scheme; BiCMOS integrated circuits; Bipolar transistors; CMOS memory circuits; CMOS process; CMOS technology; Circuit simulation; Decoding; MOS devices; Minimization methods; Random access memory;
Journal_Title :
Solid-State Circuits, IEEE Journal of
