Title :
A 7.5-ns 32 K×8 CMOS SRAM
Author :
Okuyama, Hiroaki ; Nakano, Takeshi ; Nishida, Shuichi ; Aono, Etsuro ; Satoh, Hisahiro ; Arita, Shigeru
Author_Institution :
Matsushita Electron. Corp., Kyoto, Japan
fDate :
10/1/1988 12:00:00 AM
Abstract :
A 256 K (32 K×8) CMOS static RAM (SRAM) which achieves an access time of 7.5 ns and 50-mA active current at 50-MHz operation is described. A 32-block architecture is used to achieve high-speed access and low power dissipation. To achieve faster access time, a double-activated-pulse circuit which generates the word-line-enable pulse and the sense-amplifier-enable pulse has been developed. The data-output reset circuit reduces the transition time and the noise generated by the output buffer. A self-aligned contact technology reduces the diffused region capacitance. This RAM has been fabricated in a twin-tub CMOS 0.8-μm technology with double-level polysilicon (the first level is polycide) and double-level metal. The memory cell size is 6.0×11.0 μm2 and the chip size is 4.38×9.47 mm 2
Keywords :
CMOS integrated circuits; integrated memory circuits; random-access storage; 0.8 micron; 256 kbit; 32-block architecture; 50 MHz; 50 mA; 7.5 ns; CMOS SRAM; access time; active current; data-output reset circuit; diffused region capacitance; double-activated-pulse circuit; double-level metal; double-level polysilicon; high-speed access; low power dissipation; memory cell; polycide; self-aligned contact technology; sense-amplifier-enable pulse; static RAM; twin-tub CMOS; word-line-enable pulse; CMOS technology; Capacitance; Circuit noise; Noise generators; Noise reduction; Power dissipation; Pulse circuits; Pulse generation; Random access memory; Read-write memory;
Journal_Title :
Solid-State Circuits, IEEE Journal of
