A new fast cell resequence mechanism for multipath ATM switches

Author

Heo, Jeong W. ; Sung, Dan K.

Author_Institution

Dept. of Electr. Eng., Korea Adv. Inst. of Sci. & Technol., Taejong, South Korea

Volume

3

Issue

10

fYear

1999

Firstpage

297

Lastpage

299

Abstract

A new cell resequence mechanism is proposed to restore the cell sequence in multipath ATM switches. Since the proposed mechanism uses per-VC logical queues which store only the cells belonging to the same VC, the mechanism can reduce processing time compared to conventional resequence mechanisms. The mechanism also has no limitation on the peak rate of the VCs and needs no arbitration function to select an output cell. The mechanism can be implemented using a RAM buffer, a content addressable memory/random access memory (CAM/RAM) table, a controller, etc.

Keywords

asynchronous transfer mode; buffer storage; content-addressable storage; controllers; electronic switching systems; packet switching; queueing theory; random-access storage; CAM/RAM table; RAM buffer; cell sequence restoration; content addressable memory/random access memory; controller; fast cell resequence mechanism; multipath ATM switches; output cell; peak rate; per-VC logical queues; processing time; Associative memory; Asynchronous transfer mode; Computer aided manufacturing; Delay; Quality of service; Random access memory; Read-write memory; Switches; Timing; Virtual colonoscopy;

fLanguage

English

Journal_Title

Communications Letters, IEEE

Publisher

ieee

ISSN

1089-7798

Type

jour

DOI

10.1109/4234.798023

Filename

798023