Low-loss CPW lines on surface stabilized high-resistivity silicon

Author

Gamble, H.S. ; Armstrong, B.M. ; Mitchell, S.J.N. ; Wu, Y. ; Fusco, V.F. ; Stewart, J.A.C.

Author_Institution

Sch. of Electr. & Electron. Eng., Queen´s Univ., Belfast, UK

Volume

9

Issue

10

fYear

1999

Firstpage

395

Lastpage

397

Abstract

The authors propose a solution to the surface conduction problem in silicon monolithic microwave integrated circuits (MMIC´s). An LPCVD polycrystalline silicon layer is deposited over the surface of a high-resistivity silicon wafer which is then covered with a silicon dioxide layer. The polycrystalline silicon layer effectively removes, through traps, any free electrons or holes that may have been induced at the oxide-silicon interface. The CPW lines with 1.25-μm aluminum metallization on passivated HRS substrates have an attenuation loss at 30 GHz of only 1.08 dB/cm.

Keywords

MMIC; coplanar waveguides; electron traps; hole traps; integrated circuit metallisation; losses; passivation; silicon; 1.25 micron; 30 GHz; Al metallization; LPCVD polycrystalline Si layer; Si; Si MMIC; Si-SiO/sub 2/-Al; attenuation loss; high-resistivity Si wafer; low-loss CPW lines; monolithic microwave integrated circuits; oxide-silicon interface; passivated substrates; surface conduction problem; surface stabilized Si; Aluminum; Attenuation; Charge carrier processes; Coplanar waveguides; Electron traps; MMICs; Metallization; Microwave integrated circuits; Monolithic integrated circuits; Silicon compounds;

fLanguage

English

Journal_Title

Microwave and Guided Wave Letters, IEEE

Publisher

ieee

ISSN

1051-8207

Type

jour

DOI

10.1109/75.798027

Filename

798027