An Efficient Barrier Implementation for OpenMP-Like Parallelism on the Intel SCC

This paper proposes an effective barrier synchronization implementations for shared memory-based parallel programming models (e.g. OpenMP) on the Intel SCC non-cache- coherent platform. Barrier synchronization primitives are key components of these programming models to coordinate the parallel threads. Therefore, we need an efficient implementation of the underlying synchronization algorithms to allow high-level barrier constructs for better performance. In particular, we present an efficient evaluation method to determine the overhead associated with integration of barrier algorithms that is required for OpenMP runtime libraries. We validate several implementation variants that efficiently use the network topology and SCC-specific hardware. Our experimental results for different Micro- benchmarks show significant performance improvement up to 98% for 48 cores.