DocumentCode
1255206
Title
Symbolic cover minimization of fully I/O specified finite state machines
Author
Drusinsky-Yoresh, Doron
Author_Institution
Sony Corp., Kanagawa, Japan
Volume
9
Issue
7
fYear
1990
fDate
7/1/1990 12:00:00 AM
Firstpage
779
Lastpage
781
Abstract
Currently, symbolic cover minimization is computed using multiple-valued-logic minimization. This problem, however, is computationally intractable, so less accurate heuristics are used. An alternative approach to computationally intractable problems is to reduce their generality so that the simpler problem has a tractable solution. Accordingly, a deterministic approach for the symbolic cover minimization problem for fully input/output (I/O) specified finite state machines (FSMs) is presented. A uniqueness theorem for a hierarchical extension of FSMs is proved, and the theorem is used to derive the proposed technique
Keywords
finite automata; logic arrays; minimisation of switching nets; FSMs; computationally intractable problems; deterministic approach; fully I/O specified finite state machines; heuristics; multiple-valued-logic minimization; symbolic cover minimization; Automata; Combinational circuits; Control system synthesis; Design automation; Encoding; Minimization; Programmable logic arrays; Very large scale integration;
fLanguage
English
Journal_Title
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
Publisher
ieee
ISSN
0278-0070
Type
jour
DOI
10.1109/43.55214
Filename
55214
Link To Document