Title :
A 15-ns 1-Mbit CMOS SRAM
Author :
Sasaki, Katsuro ; Hanamura, Shoji ; Ueda, Kiyotsugu ; Oono, Takao ; Minato, Osamu ; Sakai, Yoshio ; Meguro, Satoshi ; Tsunematsu, Masayoshi ; Masuhara, Toshiaki ; Kubotera, Masaaki ; Toyoshima, Hiroshi
Author_Institution :
Hitachi Ltd., Tokyo, Japan
fDate :
10/1/1988 12:00:00 AM
Abstract :
A 1-Mb CMOS static RAM with a 256 K word×4-bit configuration has been developed. The RAM was fabricated using 0.8-μm double-poly and double-aluminum twin-well CMOS technology. A small cell size of 5.2 μm×8.5 μm and a chip size of 6.15 mm×15.21 mm have been achieved. A fast address access time of 15 ns was achieved using novel circuit techniques: a PMOS-load decoder and a three-stage dynamic gain control sense amplifier combined with an equalization technique and feedback capacitances. A low active current of 50 mA at 20 MHz and low standby currents of 15 mA (TTL) and 2 μA (CMOS) were also attained
Keywords :
CMOS integrated circuits; integrated memory circuits; random-access storage; 0.8 micron; 1 Mbit; 15 mA; 15 ns; 2 muA; 20 MHz; 50 mA; CMOS SRAM; PMOS-load decoder; Si; active current; address access time; double level Al process; double poly-Si process; equalization technique; feedback capacitances; memory IC; standby currents; static RAM; three-stage dynamic gain control sense amplifier; twin-well CMOS technology; Bonding; Capacitance; Circuit synthesis; Decoding; Delay effects; MOS devices; Operational amplifiers; Random access memory; SRAM chips; Wiring;
Journal_Title :
Solid-State Circuits, IEEE Journal of
