Field-programmable-gate-array-based time-to-digital converter with 200-ps resolution

Author

Kalisz, Jozef ; Szplet, Ryszard ; Pasierbinski, Jerzy ; Poniecki, Andrzej

Author_Institution

Mil. Univ. of Technol., Warsaw, Poland

Volume

46

Issue

1

fYear

1997

fDate

2/1/1997 12:00:00 AM

Firstpage

51

Lastpage

55

Abstract

A new design of a time-to-digital converter (TDC) implemented on an FPGA chip with amorphous antifuse structures is presented. Time coding with 200-ps resolution (LSB), 10-ns range, and very short conversion time is realized by two tapped delay lines working in-a differential mode. Thanks to the local feedback loops, the output from the delay line is obtained directly in “1-out-of-N” code and then converted to 6-bit natural binary. Within the temperature range from 0°C to 45°C, the time offset at the output is constant, the resolution changes by ±0.02 LSB, and the offset-corrected integral linearity error is less than 1 LSB

Keywords

CMOS integrated circuits; amorphous semiconductors; application specific integrated circuits; delay lines; encoding; feedback; field programmable gate arrays; measurement errors; quantisation (signal); 0 to 45 C; CMOS; FPGA chip; QuickLogic; amorphous antifuse structures; conversion time; delay line; design; differential mode; field-programmable-gate-array; local feedback loops; offset-corrected integral linearity error; pASIC; resolution changes; tapped delay lines; time coding; time-to-digital converter; Amorphous materials; CMOS technology; Circuit testing; Costs; Delay lines; Field programmable gate arrays; Integrated circuit manufacture; Integrated circuit technology; Latches; Manufacturing processes;

fLanguage

English

Journal_Title

Instrumentation and Measurement, IEEE Transactions on

Publisher

ieee

ISSN

0018-9456

Type

jour

DOI

10.1109/19.552156

Filename

552156