General representation of CMOS structure transition time for timing library representation

Nonzero signal rise and fall times significantly contribute to gate propagation delay. Designers must accurately consider them when defining timing library format. Based on a design oriented macromodel of the timing performance of complementary metal-oxide semiconductor (CMOS) structures, a general representation of transition times allowing fast and accurate cell performance evaluation is presented. This representation is validated comparing calculated gate input-output transition time values with respect to standard lookup representation obtained from HSPICE simulations (BSIM3, v.3, level 69, 0.25 μm process)