Title :
An 18-ns 1-Mbit CMOS SRAM
Author :
Shimada, Hiroki ; Tange, Y. ; Tanimoto, Keishi ; Shiraishi, Michio ; Suzuki, Noriyuki ; Nomura, Toshio
Author_Institution :
Fujitsu Ltd., Kawasaki, Japan
fDate :
10/1/1988 12:00:00 AM
Abstract :
A 1-Mb (256 K×4 b) CMOS static random-access memory with a high-resistivity load cell was developed with 0.7-μm CMOS process technology. This SRAM achieved a high-speed access of 18 ns. The SRAM uses a three-phase back-bias generator, a bus level-equalizing circuit and a four-stage sense amplifier. A small 4.8×8.5-μm2 cell was realized by the use of a triple-polysilicon structure. The grounded second-polysilicon layer increases cell capacitance and suppresses α-particle-induced soft errors. The chip size measures 7.5×12 mm2
Keywords :
CMOS integrated circuits; integrated memory circuits; random-access storage; α-particle-induced soft errors; 0.7 micron; 18 ns; 256 kbit; CMOS SRAM; Si; bus level-equalizing circuit; four-stage sense amplifier; high-resistivity load cell; soft error suppression; static RAM; static random-access memory; three-phase back-bias generator; triple-polysilicon structure; CMOS technology; Capacitance; Charge pumps; Circuits; Fluctuations; Frequency; Random access memory; Ring oscillators; Standby generators; Threshold voltage;
Journal_Title :
Solid-State Circuits, IEEE Journal of
