A 25-ns low-power full-CMOS 1-Mbit (128 K×8) SRAM

Author

Chu, Sai T. ; Dikken, J. ; Hartgring, C.D. ; List, F.J. ; Raemaekers, John G. ; Bell, Simon A. ; Walsh, Brendan ; Salters, Roelof H W

Author_Institution

Philips Res. Lab., Eindhoven, Netherlands

Volume

23

Issue

5

fYear

1988

fDate

10/1/1988 12:00:00 AM

Firstpage

1078

Lastpage

1084

Abstract

A 5-V full-CMOS 1-Mb SRAM (static random-access memory) is described. The access time is 25 ns with 30-pF load, and power dissipation is 75 mW at 10 MHz and less than 1 μW in standby mode. The chip is made in a 0.7-μm twin-tub, single-poly, double-metal technology on p/p⁺ epi substrate. Cascoding of NMOS devices and special timing techniques are used to suppress hot-electron degradation. The authors describe circuit techniques that obtain low active power dissipation and high speed for a byte-wide part

Keywords

CMOS integrated circuits; integrated memory circuits; random-access storage; 0.7 micron; 1 Mbit; 10 MHz; 25 ns; 30 pF; 5 V; 75 mW; NMOS device cascoding; SRAM; access time; double-metal technology; hot electron degradation suppression; low active power dissipation; low-power; p/p⁺ epi substrate; single-poly; standby mode; timing techniques; twin-tub; CMOS technology; Circuits; Degradation; Hot carriers; MOS devices; Pins; Power dissipation; Random access memory; Semiconductor device measurement; Voltage;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.5928

Filename

5928