Reliability Evaluation for Single Event Transients on Digital Circuits

The effect of single event transient (SET) on reliability has become a significant concern for digital circuits. This paper proposed an algorithm for evaluating the reliability for SET on digital circuits, based on signal probability, universal generating function technique, and generalized reliability block diagrams. The algorithm provides an expression for the reliability of SET under consideration for the effects of logic masking, error attenuation of gates, and crosstalk effects among interconnect wires. We perform simulations of ISCAS85 circuits. The results indicate that the proposed algorithm can effectively evaluate the reliability for SET on circuits. The error attenuation of gates can increase the reliability by more than 41.6%, and the masking and crosstalk effects will improve the reliability by more than 43%.