Title :
A 690-mW 1-Gb/s 1024-b, rate-1/2 low-density parity-check code decoder
Author :
Blanksby, Andrew J. ; Howland, Chris J.
Author_Institution :
High Speed Commun. VLSI Syst. Res. Dept., Agere Syst., Holmdel, NJ, USA
fDate :
3/1/2002 12:00:00 AM
Abstract :
A 1024-b, rate-1/2, soft decision low-density parity-check (LDPC) code decoder has been implemented that matches the coding gain of equivalent turbo codes. The decoder features a parallel architecture that supports a maximum throughput of 1 Gb/s while performing 64 decoder iterations. The parallel architecture enables rapid convergence in the decoding algorithm to be translated into low decoder switching activity resulting in a power dissipation of only 690 mW from a 1.5-V supply
Keywords :
CMOS digital integrated circuits; iterative decoding; parallel architectures; 1 Gbit/s; 1.5 V; 1024 bit; 690 mW; CMOS digital integrated circuits; coding gain; decoder iterations; decoder switching activity; decoding algorithm; low-density parity-check code decoder; parallel architecture; power dissipation; soft decision; throughput; Bit error rate; Iterative algorithms; Iterative decoding; Parallel architectures; Parity check codes; Power dissipation; Product codes; Sparse matrices; Throughput; Turbo codes;
Journal_Title :
Solid-State Circuits, IEEE Journal of
