Title :
A spreadsheet simulation of logic networks
Author :
El-Hajj, Ali ; Kabalan, Karim Y.
Author_Institution :
Dept. of Electr. Eng., American Univ. of Beirut, Lebanon
fDate :
2/1/1991 12:00:00 AM
Abstract :
The authors present a method for simulating logic networks using spreadsheets. This method may be used to simulate combinational, sequential, synchronous and asynchronous networks. The characteristics of the method make it significant as an important tool in the analysis, design and test logic networks in education environments
Keywords :
circuit CAD; circuit analysis computing; computer aided instruction; digital simulation; education; logic CAD; spreadsheet programs; CAI; asynchronous; circuit CAD; circuit analysis; combinational; digital simulation; education; logic networks; sequential; spreadsheets; synchronous; Circuit simulation; Computer networks; Displays; Educational programs; Flip-flops; Hardware; Logic design; Logic gates; Logic testing; Spreadsheet programs;
Journal_Title :
Education, IEEE Transactions on
