• DocumentCode
    1256144
  • Title

    Sign extension bit minimisation algorithm for designing VLSI inner-product-processor cells for DSP applications

  • Author

    Poornaiah, D.V.

  • Author_Institution
    Transmission R&D, Indian Telephone Ind., Bangalore, India
  • Volume
    34
  • Issue
    2
  • fYear
    1998
  • fDate
    1/22/1998 12:00:00 AM
  • Firstpage
    159
  • Lastpage
    160
  • Abstract
    A new sign extension bit minimisation algorithm is presented to design efficient inner-product-processor cells with reduced area and computation time. Design examples are presented for the sake of illustration
  • Keywords
    VLSI; DSP applications; VLSI; inner-product-processor cells; sign extension bit minimisation algorithm;
  • fLanguage
    English
  • Journal_Title
    Electronics Letters
  • Publisher
    iet
  • ISSN
    0013-5194
  • Type

    jour

  • DOI
    10.1049/el:19980196
  • Filename
    653172
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1256144