Title :
A spacer patterning technology for nanoscale CMOS
Author :
Choi, Yang-Kyu ; King, Tsu-Jae ; Hu, Chenming
Author_Institution :
Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
fDate :
3/1/2002 12:00:00 AM
Abstract :
A spacer patterning technology using a sacrificial layer and a chemical vapor deposition (CVD) spacer layer has been developed, and is demonstrated to achieve sub-7 nm structures with conventional dry etching. The minimum-sized features are defined not by the photolithography but by the CVD film thickness. Therefore, this technology yields critical dimension (CD) variations of minimum-sized features much smaller than that achieved by optical or e-beam lithography. In addition, it also provides a doubling of device density for a given lithography pitch. This method is used to pattern silicon fins for double-gate metal-oxide semiconductor field effect transistors (MOSFETs) (FinFETs) and gate electrode structures for ultrathin body MOSFETs. Process details are presented
Keywords :
CMOS integrated circuits; CVD coatings; MOSFET; integrated circuit technology; nanotechnology; photolithography; plasma materials processing; sputter etching; 7 nm; CD variations; CVD film thickness; CVD spacer layer; FinFETs; chemical vapor deposition spacer layer; critical dimension variations; device density; double-gate MOSFETs; double-gate metal-oxide semiconductor field effect transistors; dry etching; e-beam lithography; gate electrode structures; lithography pitch; minimum-sized features; nanoscale CMOS; optical lithography; photolithography; sacrificial layer; silicon fins; spacer patterning technology; ultrathin body MOSFETs; CMOS technology; Chemical technology; Chemical vapor deposition; Dry etching; Lithography; MOSFETs; Optical films; Semiconductor films; Silicon; Space technology;
Journal_Title :
Electron Devices, IEEE Transactions on
