A Novel Five-Photomask Low-Temperature Polycrystalline Silicon CMOS Structure for AMLCD Application

A novel five-mask low-temperature polycrystalline silicon (LTPS) CMOS structure was verified by manufacturing the thin-film transistor test samples using the proposed five-mask LTPS CMOS process. In integrating the five-mask CMOS structure, a selective contact barrier metal formation process was developed, without additional photomask steps, to solve the issue of high-contact-resistance problem encountered inevitably in the contact between the indium tin oxide and doped polycrystalline silicon (poly-Si) source-drain layers. The five-mask CMOS technology was also confirmed by manufacturing a five-mask CMOS panel for the active-matrix liquid-crystal-display application.