• DocumentCode
    1257310
  • Title

    An implementable parallel scheduler for input-queued switches

  • Author

    Giaccone, Paolo ; Shah, Devavrat ; Prabhakar, Balaji

  • Author_Institution
    Electron. Dept., Politecnico di Torino, Italy
  • Volume
    22
  • Issue
    1
  • fYear
    2002
  • Firstpage
    19
  • Lastpage
    25
  • Abstract
    The Apsara algorithm is an input-queued switch scheduler that uses limited parallelism to find a matching in a single iteration, as compared to the O(N3) iterations of the more common maximum-weight matching algorithm. The Apsara algorithm also achieves a throughput of up to 100 percent and has very good delay properties
  • Keywords
    computational complexity; packet switching; parallel algorithms; parallel programming; pattern matching; queueing theory; Apsara algorithm; delay properties; implementable parallel scheduler; input-queued switch scheduler; input-queued switches; limited parallelism; maximum-weight matching algorithm; single iteration; throughput; Bipartite graph; Fabrics; Hardware; Internet; Packet switching; Partitioning algorithms; Round robin; Scheduling algorithm; Switches;
  • fLanguage
    English
  • Journal_Title
    Micro, IEEE
  • Publisher
    ieee
  • ISSN
    0272-1732
  • Type

    jour

  • DOI
    10.1109/40.988686
  • Filename
    988686
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1257310